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TB62705CPG/cfg/cfng toshiba bi ? cmos integrated circuit silicon monolithic TB62705CPG, tb62705cfg, tb62705cfng 8-bit shift register, latches & constant-current drivers the TB62705CPG / cfg / cfng are specifically designed for led and led display constant-current drivers. these constant-current output circuits can support the set-up of an external resistor (i out = 5~90ma). this i c is a monolithic integrated circuit designed to be used together with bi-cmos process. the devices consist of an 8-bit shift register, latch, and-gate and constant-current drivers. this devices are a product for the pb free(sn-ag). features constant-current output : current with one resistor for 5 to 90ma. maximum clock frequency : f clk = 15 (mhz) (cascade connecte operate, topr = 25c) 5v c ? mos compatible input package : dip16 ? p ? 300 ? 2.54a (TB62705CPG) ssop16 ? p ? 225 ? 1.00a (tb62705cfg) ssop16 ? p ? 225 ? 0.65b (tb62705cfng) constant output current matching: output-gnd voltage current matching output current 0.4 v 6.0% 5~40 ma 0.7 v 6.0% 5~90 ma pin connection (top view) TB62705CPG tb62705cfg tb62705cfng weight dip16 ? p ? 300 ? 2.54a : 1.11 g (typ.) ssop16 ? p ? 225 ? 1.00a : 0.14 g (typ.) ssop16 ? p ? 225 ? 0.65b : 0.07 g (typ.) 16 15 14 13 12 11 10 gnd 1 2 3 4 5 6 7 serial-in cloc k outn 9 8 enable latch outn outn outn outn outn outn outn serial-out r-ext v dd company headquarters 3 northway lane north latham, new york 12110 toll free: 800.984.5337 fax: 518.785.4725 web: www.marktechopto.com | email: info@marktechopto.com california sales office: 950 south coast drive, suite 225 costa mesa, california 92626 toll free: 800.984.5337 fax: 714.850.9314 company headquarters 3 northway lane north latham, new york 12110 toll free: 800.984.5337 fax: 518.785.4725 web: www.marktechopto.com | email: info@marktechopto.com california sales office: 950 south coast drive, suite 265 costa mesa, california 92626 toll free: 800.984.5337 fax: 714.850.9314
TB62705CPG/cfg/cfng 2005-10-06 2 block diagram timing diagram note: latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the clock signal. the data will pass through the latch circuit if the latch input is set at ?h? level, and will be retained if the input is set at ?l?. outn outn outn serial-in latch cloc k out0 out1 out3 serial-ou t enable out7 5 v 0 v 5 v 0 v off on 0 v 5 v 0 v 5 v off on off on off 5 v 0 v
TB62705CPG/cfg/cfng 2005-10-06 3 pin description pin no. pin name function 1 gnd gnd terminal for control logic 2 serial in input pin for shift register serial data 3 clock clock input terminal for data shift to up-edge. 4 latch data strobe input terminal. latches pass latch data with ?h? level input and retain data with ?l? level input. 5~12 outn output terminals 13 enable input terminal for output enable. all outputs ( outn ) go off with enable data input at "h" level and go on with data input at "l" level. 14 serial out output terminal for serial data for the next serial-in terminal. 15 r ext input terminal for connecting a resistor to regulate all output currents. 16 v dd 5-v supply pin of the ic truth table clock latch enable serial in outn serial out up h l d n d n d n 5 d n 7 d n 7 up l l d n+1 no change d n 6 up h l d n+2 d n+2 d n 3 d n 5 d n 5 down x l d n+3 d n+2 d n 3 d n 5 d n 5 down x h d n+3 off d n 5 note: outn = on if d n = h level, and outn = off if d n = l level. an external resistor is connected with r ext and gnd. be sure to administer the correct power supply voltage. input/output equivalent circuits 1. enable terminal 2. latch terminal 3. clock, serial ? in terminal 4. serial ? out terminal
TB62705CPG/cfg/cfng 2005-10-06 4 maximum ratings (ta = 25c) characteristic symbol rating unit supply voltage v dd 0~7.0 v input voltage v in 0.4~v dd + 0.4 v output current i out 90 ma output voltage v ce 0.5~17.0 v clock frequency f ck 15 mhz gnd terminal current i gnd 720 ma 1.47 (cpg type : free air, ta = 25c) power dissipation p d 0.78 (cfg / cfng type : on pcb, ta = 25c) w 85 (cpg type : free air, ta = 25c) thermal resistance r th (j a) 160 (cfg / cfng type : on pcb, ta = 25c) c / w operating temperature t opr 40~85 c storage temperature t stg 55~150 c note: cpg type: for an ambient temperature above 25c, the derating is 11.8 mw/c. cfg and cfng type: for an ambient temperature above 25c, the derating is 6.3 mw/c. recommended operating condition (ta = ? 40~85c unless otherwise stated) characteristic symbol condition min typ. max unit supply voltage v dd ? 4.5 5.0 5.5 v output voltage v out ? ? ? 15.0 v i o outn , dc 1 circuit 5 ? 88 i oh serial out ? ? 1.0 output current i ol serial out ? ? 1.0 ma v ih ? 0.7 v dd ? v dd +0.3 input voltage v il ? 0.3 ? 0.3 v dd v latch pulse width t w lat 100 ? ? ns clock pulse width t w clk 50 ? ? ns enable pulse width t w en 4500 ? ? ns set-up time for data t setup (d) 60 ? ? ns hold time for data t hold (d) 20 ? ? ns set-up time for latch t setup (l) 100 ? ? ns hold time for latch t hold (l) v dd = 4.5~5.5 v 60 ? ? ns clock frequency f ck cascade operation 10.0 ? ? mhz ta = 85c (cpg type free air) ? ? 0.82 power dissipation p d ta = 85c (cfg / cfng type on pcb) ? ? 0.40 w
TB62705CPG/cfg/cfng 2005-10-06 5 electrical characteristics (v dd = 5.0 v, ta = 25c unless otherwise stated) characteristic symbol test cir cuit condition min typ. max unit "h" level v ih ? ? 0.7 v dd ? v dd input voltage "l" level v il ? ? gnd ? 0.3 v dd v output leakage current i oh ? v oh = 15.0 v ? ? 10 a v ol ? i ol = 1.0 ma ? ? 0.4 output voltage s out v oh ? i oh = 1.0 ma 4.6 ? ? v i ol1 ? v ce = 0.7 v 34.1 40.0 45.9 output current 1 i ol2 ? v ce = 0.4 v r ext = 470 (include skew) 33.7 39.5 45.3 ma current skew ? i ol1 ? i o = 40 ma, vce = 0.4 v r ext = 470 ? ? 1.5 6.0 % i ol3 ? v ce = 1.0 v 64.2 75.5 86.8 output current 2 i ol4 ? v ce = 0.7 v r ext = 250 ? (include skew) 63.8 75.0 86.2 ma current skew ? i ol2 ? i o = 75 ma, v ce = 0.7 v r ext = 250 ? ? 1.5 6.0 % supply voltage regulation % / v dd ? r ext = 470 ? , ta = 40~85c ? 1.5 5.0 % / v pull up resistor r in (up) ? ? 150 300 600 k ? pull down resistor r in (down) ? ? 100 200 400 k ? i dd (off) 1 ? r ext = open, 7 ~ out0 = off ? 0.6 1.2 i dd (off) 2 ? r ext = 470 ? , 7 ~ out0 = off 3.5 5.8 8.0 "off" i dd (off) 3 ? r ext = 250 ? , 7 ~ out0 = off 6.5 10.7 15.0 i dd (on) 1 ? r ext = 470 ? , 7 ~ out0 = on 7.0 12.0 18.0 supply current "on" i dd (on) 2 ? r ext = 250 ? , 7 ~ out0 = on 10.0 22.0 32.0 ma
TB62705CPG/cfg/cfng 2005-10-06 6 switching characteristics (ta = 25c unless otherwise stated) characteristic symbol test cir cuit condition min typ. max unit sin outn ? 1200 1500 latch outn ? 1200 1500 enable outn ? 1200 1500 propagation delay time (?l? to ?h?) clk sout t plh ? ? 30 70 ns sin outn ? 700 1000 latch outn ? 700 1000 enable outn ? 700 1000 propagation delay time (?h? to ?l?) clk sout t phl ? ? 30 70 ns ck t w clk ? ? 20 30 pulse width latch t w lat ? ? 10 25 ns l h ? 25 50 set up time for latch h l t setup ? ? 25 50 ns l h ? 0 30 hold time for latch h l t hold ? ? 0 30 ns maximum clock rise time t r ? ? ? 10 s maximum clock fall time t f ? ? ? 10 s output rise time t or ? 300 600 1000 ns output fall time t of ? v dd = 5.0 v v ce = 0.4 v v ih = v dd v il = gnd r ext = 470 ? i out = 40 ma v l = 3.0 v r l = 65 ? c l = 10.5 pf 150 300 600 ns
TB62705CPG/cfg/cfng 2005-10-06 7 test circuit dc characteristics ac characteristics precaution on use utmost care is necessary in the design of the output line, v cc (v dd ) and gnd line since the ic may be damaged due to short-circuits between outputs, air contamination faults, or faults caused by improper grounding. outn outn outn outn
TB62705CPG/cfg/cfng 2005-10-06 8 timing waveform 1. clock ? serial out, outn 2. clock ? latch 3. enable ? outn outn (current) outn
TB62705CPG/cfg/cfng 2005-10-06 9 iout-duty cycle ( tb62705cfg / cfng ) iout-duty cycle ( tb62705cfg / cfng ) iout-duty cycle ( tb62705cfg / cfng ) iout-duty cycle ( TB62705CPG ) iout-duty cycle ( TB62705CPG ) iout-duty cycle ( TB62705CPG )
TB62705CPG/cfg/cfng 2005-10-06 10 led driver tb6270x series application note 1:cfg/cfng on pcb 2:cfg/cfng free air 3:cpg free air
TB62705CPG/cfg/cfng 2005-10-06 11 [1] output current (i out ) i out is set by the external resistor (r ? ext), as shown in fig. 1. [2] total supply voltage (vled) this device can operate on 0.4~0.7 v (v o ). when a higher voltage is input to the device, the excess voltage is consumed inside the device, which leads to power dissipation. to minimize power dissipation and loss, we recommend that the total supply voltage be set as follows: v led (total supply voltage) = v ce (t r v sat ) + v f (led forward voltage) + v o (i c supply voltage). when the total supply is too high in the light of the power dissipation of this device, an additional resistor (r) can be used to decrease the supply voltage (v o ). pattern layout [3] pattern layout this device has only one ground pin, i.e., the combined signal ground pin and power ground pin. if the ground pattern layout contains a large amount of inductance and impedance, and the voltage between the ground and latch or clock terminals exceeds 2.5 v due to switching noise, the device may not operate correctly. be sure to pay attention to pattern layout to minimize inductance. outn outn outn outn
TB62705CPG/cfg/cfng 2005-10-06 12 package dimensions weight: 1.11 g (typ.)
TB62705CPG/cfg/cfng 2005-10-06 13 package dimensions weight: 0.14 g (typ.)
TB62705CPG/cfg/cfng 2005-10-06 14 package dimensions weight: 0.07 g (typ.)
TB62705CPG/cfg/cfng 2005-10-06 15

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